1. Technical Field
The present invention relates to an error correction circuit and an error correction method, in particular an error correction circuit and an error correction method to correct an error that occurs when an input signal is input to a logic circuit.
2.Background Art
Conventionally, errors sometimes occur in data stored in internal RAMs (Random Access Memories) of LSI (Large Scale Integration) circuits and in data held in registers and the like due to causes such as soft errors. For such errors, it has been possible to perform error correction and error detection by adding an ECC (Error Correction Code), a parity, and/or the like to the relevant data. For example, a soft error may occur when a neutron(s) or the like causes an electrical charge in the medium of the material of an LSI chip.
Meanwhile, a typical logic circuit that performs internal control of an LSI device has a complicated configuration. Therefore, although it has been possible to perform error detection processing on a logic circuit, it has been very difficult to perform error correction processing on a logic circuit. Techniques relating to error detection processing for logic circuits are described hereinafter.
FIG. 6 shows a general idea for detecting an error(s) by redundancy of a logic circuit in an LSI device. An LSI device shown in FIG. 6 compares outputs of equivalent logic circuits arranged in parallel to determine whether or not there is an error(s) in the outputs from the logic circuits. FIG. 7 shows a general idea for detecting an error by using parity prediction. An LSI device shown in FIG. 7 supplies a parity bit(s) as well as an input signal(s) to a logic circuit. It compares an output signal output from the logic circuit with the parity bit, and thereby determines whether or not there is an error in the output from the logic circuit based on the parity.
However, both the redundancy of a logic circuit and the parity prediction are a technique for detecting an error as described above, and therefore they cannot perform error correction processing. In recent years, as the LSI manufacturing process has been miniaturized, it is conceivable that the number of cases where an error occurs even in the internal logic circuit of an LSI device could become larger. Therefore, techniques capable of not only detecting an error that has occurred in the internal logic circuit of an LSI device but also correcting the error are important.
Note that it is conceivable to realize a circuit that performs equivalent operations to those of a desired logic circuit and is equipped with an error correction function by a PLA (Programmable Logic Array), and substitute this PLA circuit for the logic circuit.
However, there is a problem in the above-mentioned configuration using a PLA that configuring the PLA is complicated. That is, to obtain the equivalent operations to those of the desired logic circuit, the user needs to configure the entire circuit configuration information including the error correction processing before or during circuit operations. Further, the user also needs to grasp the operations of the desired logic circuit. Therefore, there has been a problem that users have to go through a lot of trouble.
The present invention has been made to solve these problems, and an exemplary object thereof is to provide an error correction circuit capable of correcting an error with a simple configuration.